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MCP6S21/2/6/8
DIGITAL CHARACTERISTICS
Electrical Specifications: Unless otherwise indicated, T A = +25°C, V DD = +2.5V to +5.5V, V SS = GND, V REF = V SS , G = +1 V/V,
Input = CH0 = (0.3V)/G, CH1 to CH7 = 0.3V, R L = 10 k ? to V DD /2, C L = 60 pF, SI and SCK are tied low, and CS is tied high.
Parameters
Sym
Min
Typ
Max
Units
Conditions
SPI Inputs (CS, SI, SCK)
Logic Threshold, Low
Input Leakage Current
Logic Threshold, High
V IL
I IL
V IH
0
-1.0
0.7V DD
—
—
—
0.3V DD
+1.0
V DD
V
μA
V
Amplifier Output Leakage Current
—
-1.0
—
+1.0
μA
In Shutdown mode
SPI Output (SO, for MCP6S26 and MCP6S28)
Logic Threshold, Low
Logic Threshold, High
V OL
V OH
V SS
V DD -0.5
—
—
V SS +0.4
V DD
V
V
I OL = 2.1 mA, V DD = 5V
I OH = -400 μA
SPI Timing
Pin Capacitance
Input Rise/Fall Times (CS, SI, SCK)
Output Rise/Fall Times (SO)
CS high time
SCK edge to CS fall setup time
CS fall to first SCK edge setup time
SCK Frequency
SCK high time
SCK low time
SCK last edge to CS rise setup time
CS rise to SCK edge setup time
SI set-up time
SI hold time
SCK to SO valid propagation delay
CS rise to SO forced to zero
C PIN
t RFI
t RFO
t CSH
t CS0
t CSSC
f SCK
t HI
t LO
t SCCS
t CS1
t SU
t HD
t DO
t SOZ
—
—
—
40
10
40
—
40
40
30
100
40
10
—
—
10
—
5
—
—
—
—
—
—
—
—
—
—
—
—
—
2
—
—
—
—
10
—
—
—
—
—
—
80
80
pF
μs
ns
ns
ns
ns
MHz
ns
ns
ns
ns
ns
ns
ns
ns
All digital I/O pins
MCP6S26 and MCP6S28
SCK edge when CS is high
SCK edge when CS is high
MCP6S26 and MCP6S28
MCP6S26 and MCP6S28
Channel and Gain Select Timing
Channel Select Time
t CH
—
1.5
—
μs
CHx = 0.6V, CHy =0.3V, G = 1,
CHx to CHy select
CS = 0.7V DD to V OUT 90% point
Gain Select Time
t G
—
1
—
μs
CHx = 0.3V, G = 5 to G = 1 select,
CS = 0.7V DD to V OUT 90% point
Shutdown Mode Timing
Out of Shutdown mode (CS goes
high) to Amplifier Output Turn-on
t ON
—
3.5
10
μs
CS = 0.7V DD to V OUT 90% point
Time
Into Shutdown mode (CS goes high)
to Amplifier Output High-Z Turn-off
t OFF
—
1.5
—
μs
CS = 0.7V DD to V OUT 90% point
Time
POR Timing
Power-On Reset power-up time
Power-On Reset power-down time
t RPU
t RPD
—
—
30
10
—
—
μs
μs
V DD = V POR - 0.1V to V POR + 0.1V,
50% V DD to 90% V OUT point
V DD = V POR + 0.1V to V POR - 0.1V,
50% V DD to 90% V OUT point
Note 1: Not tested in production. Set by design and characterization.
2: When using the device in the daisy chain configuration, maximum clock frequency is determined by a combination of
propagation delay time (t DO ≤ 80 ns), data input setup time (t SU ≥ 40 ns), SCK high time (t HI ≥ 40 ns), and SCK rise and
fall times of 5 ns. Maximum f SCK is, therefore, ≈ 5.8 MHz.
DS21117A-page 4
? 2003 Microchip Technology Inc.
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